Integrated circuits are vulnerable to a phenomenon generically referred to as electrostatic discharge ("ESD"). During handling, integrated circuits can build up relatively large static charges on their inputs. These charges, if not properly compensated for, may flow or "discharge" to a lower potential region. Discharging in this way produces large electric fields within the transistors that are immediately connected to the various inputs and outputs of a particular circuit. High electric fields in turn, produce high temperature gradients and ultimately yield thermal electrode migration ("TEM") within the transistor. TEM describes how a transistor fails when the contact to a doped source/drain region separates from the region. TEM causes irreversible circuit failures. ESD and TEM become more severe as circuits dimensions decrease. The smaller the dimension of, for instance, a doped drain region, the higher the electric field will be per charge. As a result, new semiconductor technologies require more effective designs to overcome these problems.
Heretofore, electronics designers have relied on the inherent diode existing between the source/drain region and the grounded substrate of a NMOS FET or of a n-channel FET in a CMOS transistor pair. The p-n junction in such a transistor protects the contact from up to 18 volts of charge buildup. After approximately that amount of buildup, however, ESD occurs from the drain to the ground plane through the substrate. Some designs modify certain characteristics of the drain to improve ESD performance. In particular, in some transistors may increase the distance between the affected contact and the gate. This modification increases the ESD protection up to a distance of approximately 6 .mu.m. Beyond F6 .mu.m, however, the ESD performance flattens and ultimately decreases as electrostatic charge shorts to the p substrate material at a different point. Such a transistor also suffers from lower gain as the larger source-drain region increases resistivity. Other designers simply increase the volume of the n drain to increase the area of the drain-substrate interface. Unfortunately, this also increases the resistance and capacitance of the transistor. The transistor, therefore, suffers from a lower gain and a lower maximum switching speed.
Therefore, a need exists for a transistor having a greater breakdown voltage between the source-drain regions and the corresponding p substrate with no loss of switch performance.